1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method of the semiconductor device, and particularly to a semiconductor device using an SOI substrate.
2. Description of the Related Art
SOI (Silicon On Insulator) devices are structured such that a silicon substrate layer and a thin film silicon layer formed over it (hereinafter called an SOI layer) are separated and insulated by a buried oxide film (BOX layer). By this means, insulating separation between adjacent elements can be easily achieved, and further because a parasitic thyristor is not formed via the silicon substrate layer, a latch-up phenomenon is prevented from occurring. Yet further, constructing transistors in the SOI layer on the insulating film is effective in suppressing the so-called short-channel effect that as transistors become finer, power consumption increases. Still further, because their junction capacitance is smaller than that of transistors of a bulk structure, transistors formed of the SOI structure can operate at higher speed. Since having many excellent characteristics as such, transistors of the SOI structure are expected to be able to achieve higher speed and lower power consumption as compared with conventional semiconductor elements formed in a bulk substrate.
Attempts to apply wafers having this SOI structure (hereinafter called SOI substrates) to UV sensors are being made. Because conventional UV sensors use a compound semiconductor such as gallium nitride, it is difficult to incorporate a peripheral circuit in the same chip. Further, as to UV sensors using a silicon substrate, because they have sensitivity to light over a wide range of wavelengths, there is the problem that an optical filter for blocking visible light is necessary, resulting in production costs being high and the sensitivity being low. As to UV sensors using an SOI substrate, a peripheral circuit such as an operational amplifier can be incorporated in the same chip, and because a photodiode having sensitivity only to UV light can be formed by thinning the SOI layer, they have the merit that a good spectral sensitivity characteristic is obtainable without using an optical filter.
Meanwhile, wafer-level chip size packages (hereinafter called W-CSP) that realize packages of the same size as chips are known as a technology to achieve the miniaturization of semiconductor packages. W-CSP are packages of a new concept wherein the entire assembly process finishes with them remaining in a wafer state.
In W-CSP, a penetrating electrode structure is adopted because the improvement in reliability and the miniaturization of devices can be achieved therewith. Usually, electrodes for a semiconductor device to send/receive signals to/from the outside are formed on the same surface that the semiconductor element is formed in. In contrast, as to the penetrating electrodes, through holes are formed extending from the back side of a chip in a thickness direction of the chip by fine processing technology, and conductor lines are formed inside the through holes, and by connecting the conductor lines to front electrodes, it becomes possible to send/receive signals to/from the back side of the chip, which is usually not used. Further, by laying a plurality of chips one over another with the penetrating electrode technique to form signal transfer paths along a thickness direction of the chips, line lengths are shortened compared with conventional wiring, and thus packaging density can be significantly improved as well as higher speed and higher reliability being achieved.
In these years, optical sensors such as a UV sensor and an image sensor are mounted in mobile apparatuses such as mobile phones, and there is a demand that their packages become further smaller in size. In optical sensors, in the case of providing external terminals on the light receiving surface side, it is necessary to provide terminals in an area outside a light receiving area. Hence, an area on which to provide external terminals that is separate from the light receiving area needs to be secured on a surface of sensor devices, necessarily resulting in an increase in chip size, and thus, it is difficult to meet the demand for the miniaturization of packages. Accordingly, for packages of optical sensors, W-CSP having the penetrating electrode structure is being adopted. That is, in the W-CSP having the penetrating electrode structure, because external terminals are formed on the surface opposite to the light receiving surface, the external terminals can be arranged without being affected by the arrangement of the light receiving area, and also the demand for the reduction of package sizes can be met.
However, packaging SOI devices in the W-CSP structure having penetrating electrodes causes a new problem. That is, in the W-CSP having the penetrating electrode structure, insulating films are usually formed in between a semiconductor substrate and penetrating electrodes, back side lines, and external terminals, which are insulated thereby. Hence, where an SOI substrate is used as the semiconductor substrate, the silicon substrate layer is not connected to any external terminal, thus being floating in potential. If the potential of the silicon substrate layer is floating, the operation of the circuit formed in the SOI layer may become unstable, causing a malfunction. Hence, the potential of the silicon substrate layer of the SOI substrate needs to be fixed.
As a method of fixing the silicon substrate layer of an SOI substrate to ground potential, a configuration where a chip is mounted on a lead frame fixed to ground potential via a conductive adhesive is disclosed in, e.g., Japanese Patent Application Laid-Open Publication No. H07-335811 (Reference 1).
Meanwhile, in Japanese Patent Application Laid-Open Publication No. H11-354631 (Reference 2), there is disclosed the configuration of a semiconductor device where a conductive layer leading from a surface of the SOI layer through the SOI layer and the BOX to the silicon substrate layer is formed and where a substrate potential fixing electrode electrically connected to the conductive layer is formed on the surface of the SOI layer.
However, since the W-CSP having penetrating electrodes is usually mounted on a mounting board via solder balls constituting external terminals, a mounting method which connects the back side of the SOI substrate directly to a lead frame cannot be used. That is, it is difficult to adopt the configuration described in Reference 1 to the W-CSP having the penetrating electrode structure.
Further, the configuration described in Reference 2 cannot be applied, as it is, to packages having external terminals on the back side of the SOI substrate because the substrate potential fixing electrode is formed on the surface of the SOI layer. That is, if the structure described in Reference 2 is applied to the W-CSP having penetrating electrodes, a voltage supply path other than the penetrating electrodes such as one made by wire-bonding will be needed to give a potential to the substrate potential fixing electrode formed on the surface of the chip, resulting in a reduction in the merit of adopting the penetrating electrode structure. Further, since the SOI substrate needs to be etched to form a contact hole reaching the substrate layer, a space where to form the contact hole needs to be secured separately, which may cause an increase in chip size.